The invention relates to a circuit arrangement for decimal arithmetic for performing decimal subtraction at a high speed.
In a conventional decimal arithmetic circuit arrangement, decimal arithmetic is usually performed by applying binary-coded decimal (BCD) numbers to a binary addition subtraction circuit. In the conventional circuit arrangement, when a borrow occurs at the most significant digit position of a minuend because the subtrahend is larger than the minuend, it becomes necessary to take a correction step of obtaining the 10's complement of the result of the subtraction. Whether such a correction step should be taken is usually determined by a conditional branch microinstruction.
An example of the conventional circuit arrangement for decimal arithmetic is disclosed in Section 6.6, pp. 230-243 of a book entitled "Computer Organization and Microprogramming" by Yaohan Chu, published in 1972 from Prentice-Hall, Inc. However, the conventional circuit arrangement is disadvantageous in that, as described in more detail hereinafter, when the flow of an arithmetic processing is branched out by a conditional branch microinstruction, the pipeline processing is disturbed in the circuit arrangement which increases the time required for the arithmetic processing.
An object of the invention is, therefore, to provide a circuit arrangement for decimal arithmetic free from the above-mentioned disadvantages of the conventional arrangement.